While the DDS design solves the problem of matching the chromatic scale, it does so by sacrificing resolution at higher frequencies. For example, at C8 (the highest key on an 88-key keyboard) the phase adjustment (addend) is 1797877 yielding only 5.6 samples per cycle, far less than the goal of 256 samples per cycle. I have not determined the impact this will have on the sound.

With a sample rate of 10 Mhz, the highest note with a sample rate greater than or equal to 256 is F2. Each doubling of the clock frequency raises this by an octave; however, the master clock is the sample rate multiplied by the number of channels, so this strategy quickly becomes untennable using 74HC series devices. If 8 74HCT283 devices are used for the 32-bit adder, the design probably could not support a master clock frequency higher than 20 MHz (50 nanosecond cycle time).

The devices used throughout the design are dual-port RAMs (DPRAMs) except the phase accumulator RAM. This is for convenience to allow a microprocessor to modify the memories without a lot of bus control logic.

The phase adjustment (addend) memory and phase accumulator memory could be as small as 16xN but no such devices are currently in production. The 74LS219 was a 16x4 RAM but an HC/HCT version of this device was never produced. The 74HCT670 4x4 register file could be used to support a mimum of 4 channels.

One alternative would be to implement the entire design excluding the DAC in a Field Programmable Gate Array (FPGA). For example, the Lattice iCE40UP5K family prices range from $5 to $8 and have enough internal RAM to support as many as 16 channels. There is probably enough RAM to allow multiple waveshapes in memory and select a different waveshape based on the desired pitch. Here is a design of a single channel DDS. Click on an image to download a full resolution TIFF file.

A summing network would need to be pipelined to account for the delays in a tree of adders. Here is a design of a 16-channel pipelined summing network. Click on an image to download a full resolution TIFF file.

• Design Document
• DDS Block Diagram
• Timing Diagram
• Sequencer Block Diagram

• DDSTool.java
• Note.java
• DDSTool.jar